1. Technical Field
The present invention relates generally to datapath systems, and more particularly, to a method, system and program product for building an automated datapath system generating tool.
2. Related Art
As silicon technologies offer constantly increasing levels of integration, application specific integrated circuit (ASIC) designers are continually challenged to increase productivity and produce larger and larger designs with the same or less resources. Use of ASIC macros that each include a predetermined structure for a part of an ASIC and can be used repetitively is one technique for addressing this challenge. Use of such ASIC macros eliminates the need for the ASIC designer to design sections of the chip, and therefore improves productivity. As a result, design reuse methodology involving the use of ASIC macros provided by legacy designs, third party vendors or the ASIC vendor, has become an essential part of ASIC design.
The provider of such ASIC macros is challenged to provide a product that has been partitioned to provide maximum flexibility in meeting a wide range of requirements. The goal is to provide a single macro design that can be used in a wide range of ASIC designs without modification. Meeting this challenge requires the macro function to be partitioned such that some work is left to the ASIC designer to customize the configuration of the macro for a given application. For instance, an ASIC SRAM macro may be available in sizes up to 16,000 words by 128 bits wide because of subarray sizes that are reasonable to build as stand-alone cells in the technology. As a result, an application requiring a 32,000 by 256 bit memory must interconnect four such macros. In this case, the actual interconnection of macros would be manually performed by an ASIC designer. Another more complex application where a similar configuration is required relates to a bit-sliced datapath system including multiple high-speed serial input/output (I/O) channels, clock domain crossing first-in-first-out (FIFO) macros, and protocol logic macros. A bit-sliced datapath system relates to subsystems that support a variety of protocols including, for example, Infiniband, XAUI, PCI Express, Serial ATA, etc. To facilitate maximization of the use of ASIC macros, these subsystem components are supplied as separate macros such as: various High Speed Serializer/Deserializer (SerDes) macros supporting the basic serial I/O function (each macro supports N1 channels); separate clock domain crossing FIFO macros (each macro supports N2 channels); and separate protocol logic macros (each macro requires connection to N3 channels). Generically, N1, N2, and N3 are typically not equal. Also, the protocol logic macros may be further partitioned such that separate macros are provided for various protocol layers.
Subsystems as described above have typically required the ASIC designer to research information in the documentation for the ASIC macros, determine proper component interconnections, and then incorporate these components into the ASIC design as netlist instantiations. These macros also include many programmable functions and features that are used differently by each user depending on their application, which requires different pin connections or control. Many of these pins require connections to be made consistent with requirements imposed to support manufacturing test or IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture (hereinafter “IEEE 1149.1”). It is not uncommon for the resulting subsystem to require the ASIC designer to make thousands of interconnections to integrate the ASIC macros. Design in this manner is tedious and error-prone, and often requires considerable support from the ASIC macro provider. However, because these interconnections are different for each ASIC design, ASIC macros cannot be supplied at a higher level of integration without defeating the goal of design reuse.
Various software products are available to automate subsystem interconnections for specific types of subsystems. For example, various suppliers of ASIC macros also supply “wrappers” with these macros to interconnect the macros and/or make appropriate test connections. Many of these suppliers have tools that automate the generation of these wrappers. However, these tools are generally dependent on hard-coded knowledge of specific types of subsystems, and thus are not extensible to more complex subsystems, or other target subsystems. There are software tools currently available that use knowledge derived from databases and are therefore more extensible. However, these tools rely on conventional bundling (as described below) to make interconnections. As will be described, such schemes are not optimal for the interconnection of datapath i/o systems, especially bit-sliced datapath systems.
High-level design languages (HDLs) exist that allow grouping of multiple ports of various classes on an ASIC macro into a structured class declaration, assignment of a type, and making one connection for all pins. For instance, a bus class can be declared that includes as elements of the structure all of the data, address, and control pins associated with the bus. The entity declaration can then make use of this class in pin definitions, and pins can be declared using this class. Unfortunately, this type of bundling is limited in that the pins must be assigned as an entire unit—so all pins have to be on the first macro and on the second macro. This conventional bundling technique reduces the number of apparent pins on the entity, and reduces the number of interconnections that must be made between components in the design. For subsystems containing cores for which the prevalent interconnections are busses, this technique can substantially reduce the number of interconnections. In a datapath system, data is bit sliced, which means there is no one-to-one correspondence between macro pins. Accordingly, conventional bundling is less effective in datapath systems because macros in such systems often consist of a myriad of sideband control/status pins that do not lend themselves to traditional bundling. In addition, conventional bundling does not permit the bundle of pins to be bit sliced across multiple macro instantiations.
Conventional bundling, as described above, also requires rigid pin declarations as to the contents of the bundle, and requires explicit interconnection of one bundled pin to another bundled pin. Some software tools have used pin attributes and algorithmic approaches to somewhat relax the need for rigid pin declarations. These tools use the equivalent of type names, indices, and pin characteristics to bundle pins. However, these tools still requires explicit interconnection of one bundled set of pins to another bundled set of pins. Some of these tools can, however, apply class-type inference rules based on pin attributes within the bundles to determine the correct interconnections. This allows the bundle definition to be less rigid. For instance, a bundle containing a 16-bit data bus can be connected to a peripheral unit, which only supports an 8-bit data bus, and the correct interconnection is inferred.
In view of the foregoing, there is a need in the art for a method to more fully leverage ASIC macros that does not suffer from the problems of the related art.